F0303237

module top; 

wire A, B, Cin, c1, c2, c3, sum, Cout;

system_clock #400 clock1(Cin); 

system_clock #200 clock2(A);

system_clock #100 clock3(B);

xor(c1, A, B);

and(c2, A, B);

xor(sum, c1, Cin);

and(c3, c1, Cin);

xor(Cout, c3, Cin);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule